01 Selected work
Things I’ve built.
RTL, accelerators, and firmware. Every project links to its repository, where you’ll find the block diagrams, waveforms, and source.
P.01
Team of 5 · Control & runtime lead
RAVEN — RISC-V-controlled FPGA neural processing unit
Led control and runtime for a 5-person team building an INT8 NPU on the Ultra96-V2, integrating a MicroBlaze V RISC-V core, AXI4-Lite interconnect, AXI DMA, and interrupt controller.
- Array
- 8×8 MAC
- Peak
- 6.4 GMAC/s
- Timing
- 100 MHz
- Verify
- 657 checks
Deep dive
- Control plane. SystemRDL-generated 36-register CSR block (RTL, C headers, docs), a depth-4 command queue, and a control FSM with bank interlock, watchdog, and 11 error codes.
- Bare-metal runtime. A ≤48 KiB C runtime (HAL, drivers, model loader) running AD01, DS-CNN, and MobileNetV1-VWW from one binary.
- Performance & verification. Overlapped DMA and compute across ping-pong banks, cutting command issue from 22 MMIO writes to ~5 per tile (≤2 µs interrupt-to-ISR latency). Verified with a 657-check testbench and on-board fault injection: 0 mismatches vs. the TFLite-Micro INT8 reference.
P.02
UF / Apple-sponsored hardware design contest
BNN FPGA accelerator — binary neural network for MNIST
Designed and optimized a parameterized, pipelined binary neural network classifier targeting the SFC 784→256→256→10 topology, with AXI4-Stream config, input, and output interfaces.
- fMax
- 670.69 MHz
- Target
- UltraScale
- Throughput
- 21,545 out/s
- Tests
- 50 / 50 pass
Deep dive
- Timing optimization. Reached 670.69 MHz fMax on Xilinx UltraScale via pipelining, retiming, and LUT reduction.
- RTL architecture. Custom configuration manager, neuron processors (PN=8, PW=8), and a memory hierarchy across 3 hidden/output layers.
- Verification. Parameterized testbench with functional coverage, assertions, and a behavioral reference model: 100% pass rate across 50 test cases at 21,545 outputs/sec average throughput.
P.03
Personal project
FPGA CNN accelerator — pipelined 3×3 RGB convolution
A fully pipelined accelerator for 3×3 RGB convolution with a custom sliding-window buffer and packed RGB memory format, producing one output pixel per clock after pipeline fill.
A personal project, separate from the CNN accelerator I developed for my research at the SmartSystems Lab. It provided much of the framework for the research design.
- Kernel
- 3×3 RGB
- Rate
- 1 px / cycle
- Golden
- Python model
- HDL
- VHDL
Deep dive
- Pipelined datapath. One output pixel per clock cycle after the initial pipeline fill latency.
- Custom memory architecture. A sliding-window buffer and packed RGB format reuse pixel data across convolution windows, cutting memory accesses and simplifying address generation.
- Verification. A cycle-accurate Python reference model generates golden vectors; a VHDL testbench with valid-bit tracking checks data integrity across every pipeline stage.
P.04Architecture
32-bit MIPS microarchitecture
A 5-stage pipelined MIPS processor with a hardware forwarding unit and hazard detection unit that resolve data and control dependencies without software-inserted bubbles.
Deep dive
- 5-stage pipeline. Classic fetch, decode, execute, memory, write-back structure.
- Hazard resolution. Forwarding resolves RAW dependencies; the hazard detection unit stalls only when needed (load-use); taken branches flush the front end.
- Integration. Word-aligned instruction and data memories, register file, and a custom ALU for arithmetic, logical, and branch operations.
P.05Architecture
Cache replacement analysis
A multi-threaded C++ cache simulator driven by ChampSim traces, comparing LRU and LFU replacement policies across cache sizes and workloads.
Deep dive
- Simulator. Parses ChampSim traces and runs LRU and LFU simulations in parallel, using O(1) hash-map and linked-list implementations.
- Comparison. Measures hit/miss rates across configurable cache sizes on real CPU workload traces.
- Analysis. Compares hit rates across sizes and workloads to show which policy suits which access patterns.
P.06Systems
Jetson Nano kernel module + CUDA
A custom Linux kernel module exposing an ioctl interface to user space, paired with a CUDA kernel that offloads the same image processing to the GPU.
Deep dive
- Kernel development. Registers a misc character device with an ioctl handler that receives an image path from user space and modifies the image data in kernel space.
- CUDA acceleration. A CUDA kernel performs per-pixel image processing on the GPU, mirroring the CPU-side kernel-module implementation for comparison.
- Integration. A user-space CUDA application loads image data, copies it to GPU memory, runs the kernel, and copies results back.
P.07Embedded
Ray tracing on Cortex-M7
A ray-tracing engine ported to the Teensy 4.1 (600 MHz Cortex-M7), rendering 3D sphere scenes to an ILI9341 display within tight memory limits.
Deep dive
- Embedded optimization. Single-precision floats, object reuse, and reduced scene complexity to fit a full ray tracer on a microcontroller with limited RAM.
- Render pipeline. Sphere intersection, Lambertian, metal, and dielectric materials, and camera rays in an embedded runtime.
- Tuning. Precision and recursion depth traded against image fidelity and render time.